On Cyclic Scan Integrity Tests for EDT-based Compression

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test,...

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Bibliographic Details
Main Authors: Cheng, Wu-Tung, Mrugalski, Grzegorz, Rajski, Janusz, Trawka, Maciej, Tyszer, Jerzy
Format: Conference Proceeding
Language:English
Subjects:
Cloud computing
E-beam test
Encryption
laser voltage imaging
logic BIST
Middleboxes
Payloads
repeated scan integrity tests
scan cell diagnosis
Servers
test compression
Online Access:Request full text
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Summary:The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.
ISSN:2375-1053
DOI:10.1109/VTS.2019.8758670