Low-Routing-Complexity Convolutional/Turbo Decoder Design for Iterative Detection and Decoding Receivers

A highly hardware-shared convolutional/turbo decoder for iterative detection and decoding (IDD) receivers is presented here. Furthermore, parallel dual-mode decoding kernels are proposed to alternatively decode the long-term evolution (LTE)-compatible convolutional codes (CCs) and turbo codes (TCs)...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-11, Vol.66 (11), p.4476-4489
Main Authors: Lin, Cheng-Hung, Hsieh, Ching-Wen
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
CMOS
Codes
Complexity
Convolutional code (CC)
Convolutional codes
Decoders
Decoding
Detectors
Integrated circuits
Iterative decoding
iterative detection and decoding (IDD)
Kernel
Kernels
maximum <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">a-posteriori (MAP) algorithm
Measurement
Receivers
turbo code (TC)
Turbo codes
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Summary:A highly hardware-shared convolutional/turbo decoder for iterative detection and decoding (IDD) receivers is presented here. Furthermore, parallel dual-mode decoding kernels are proposed to alternatively decode the long-term evolution (LTE)-compatible convolutional codes (CCs) and turbo codes (TCs) using a parity-enhanced soft-input soft-output maximum a-posteriori algorithm. However, decoding the high-constraint-length CC results in complicated interconnections among the parallel decoding kernels and unroutable back-end chip implementation. Therefore, a minimized global route (MGR) design is proposed for the dual-mode decoder to further simplify the global data transfers and reduce the routing complexity. Using a 40-nm CMOS process, the proposed dual-mode decoder achieves a 48% area reduction compared with the individual single-mode TC and single-mode CC decoders. The global routing length of the proposed decoding kernels is reduced by 32% using the MGR design. Because of the feasible placements and routing, the proposed dual-mode decoder is implemented in an application-specific integrated circuit of 2.88-mm 2 core area at the maximum operating frequency of 364 MHz. For the LTE-based IDD receiver, the proposed dual-mode decoder achieves high area efficiencies of 0.21 and 0.35 bits/mm 2 for the TC and CC decoding, respectively.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2927362