A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power

This paper presents an inductor-less fractional-N clock multiplier with low integrated jitter and power. The architecture is based on a multiplying delay locked loop with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique which limits the ji...

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Bibliographic Details
Main Authors: Santiccioli, Alessio, Mercandelli, Mario, Lacaita, Andrea L., Samori, Carlo, Levantino, Salvatore
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Delays
DTC
Frequency locked loops
Injection-Locking
Jitter
Low-Jitter
Low-Power
MDLL
Multiplexing
Multiplying Delay-Locked Loop
Oscillators
Phase locked loops
PLL
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Summary:This paper presents an inductor-less fractional-N clock multiplier with low integrated jitter and power. The architecture is based on a multiplying delay locked loop with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique which limits the jitter added to the reference signal, at no additional power penalty. The prototype, implemented in 65nm CMOS, covers the 1.6-to-3.0-GHz range and achieves an absolute RMS jitter (integrated from 30kHz to 30MHz) of 397fs at 2.5mW power consumption, leading to a jitter-power Figure of merit of -244dB. In-band fractional spurs are as low as -51.5dB and the occupied core area is 0.0275mm 2 .
ISSN:2152-3630
DOI:10.1109/CICC.2019.8780235