A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET

Increased transceiver throughput requires clock sources of ever greater fidelity. This work demonstrates a digital PLL with 143fs rms jitter (in 1kHz-100MHz band), enabled by a low noise, 13.5-15.7GHz digitally controlled oscillator providing fine resolution (1.2MHz/LSB) without relying on coarse ba...

Full description

Saved in:
Bibliographic Details
Main Authors: Pfaff, Dirk, Abbott, Robert, Wang, Xin-Jie, Zamanlooy, Babak, Moazzeni, Shahaboddin, Smith, Raleigh, Lin, Chih-Chang
Format: Conference Proceeding
Language:English
Subjects:
Bang-Bang PLL
calibrated current source
class-C DCO
Clocks
inversion mode varactor
Jitter
limit cycle
look-ahead filter
PAM-4
Phase locked loops
Phase noise
transceiver clock generation
Tuning
Varactors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Increased transceiver throughput requires clock sources of ever greater fidelity. This work demonstrates a digital PLL with 143fs rms jitter (in 1kHz-100MHz band), enabled by a low noise, 13.5-15.7GHz digitally controlled oscillator providing fine resolution (1.2MHz/LSB) without relying on coarse band selection. The TDC-less PLL eliminates limit cycles by substantial reduction of the loop latency, achieved by a look-ahead digital loop filter operated at 3.5GHz, or 10x the reference clock frequency. The 7nm FinFET implementation measures 0.06mm 2 and consumes 40mW.
ISSN:2152-3630
DOI:10.1109/CICC.2019.8780247