An adder using charge sharing and its application in DRAMs

This paper develops a novel technique which uses charge sharing as a method to perform addition in memory arrays. DRAM cells are conventionally used as storage elements and their data read through charge sharing. In our approach, DRAM cells are used as arithmetic units, thus saving area and power co...

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Bibliographic Details
Main Authors: Hak-Soo Yu, Songjun Lee, Abraham, J.A.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Application software
Arithmetic
Circuit noise
CMOS logic circuits
Jacobian matrices
Logic circuits
Microprocessors
Random access memory
Voltage
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Description
Summary:This paper develops a novel technique which uses charge sharing as a method to perform addition in memory arrays. DRAM cells are conventionally used as storage elements and their data read through charge sharing. In our approach, DRAM cells are used as arithmetic units, thus saving area and power consumption in system-on-silicon applications. An adder in DRAM is designed, and its HSPICE simulation results are presented to show the viability of the proposed scheme.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2000.878301