Impact of silicide process on eFuse programming, reliability and ruggedness in RF BiCMOS Technology

0.35um SiGe BiCMOS wafers were fabricated using Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances and behavior during programming betwe...

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Bibliographic Details
Main Authors: Gebreselasie, Ephrem, Loiseau, Alain, Ngu, Yves, Mcallum-Cook, Ian
Format: Conference Proceeding
Language:English
Subjects:
CoSi
Discrete Device
eFuse ESD
NiSi
PtSi
TiSi
Online Access:Request full text
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Summary:0.35um SiGe BiCMOS wafers were fabricated using Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances and behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. This work demonstrates the compatibility of eFuse technology across a range of process technology nodes, as well as its robustness in high reliability applications.
ISSN:2376-6697
DOI:10.1109/ASMC.2019.8791749