Dynamic-threshold CMOS SRAM cells for fast, portable applications

A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transit...

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Bibliographic Details
Main Authors: Bhavnagarwala, A.J., Kapoor, A., Meindl, J.D.
Format: Conference Proceeding
Language:English
Subjects:
Boosting
Capacitance
Geometry
Inverters
Large scale integration
MOSFET circuits
Random access memory
Subthreshold current
Threshold voltage
Transistors
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Summary:A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transition triggered pulses on source and substrate terminals of cell inverter transistors that share a common WL.
ISSN:1063-0988
DOI:10.1109/ASIC.2000.880764