System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration

• Main Authors: Chen, Ming-Fa, Chen, Fang-Cheng, Chiou, Wen-Chih, Yu, Doug C.H.
• Format: Conference Proceeding
• Language: English
• Subjects: 3DIC; 5G/AI; Bandwidth; Bonding; data bandwidth; Flip-chip devices; InFO_PoP; PI/SI; Reliability; SoIC; Stacking; sub-10μm IO; Three-dimensional displays; Through-silicon vias
• ISSN: 2377-5726
• DOI: 10.1109/ECTC.2019.00095

A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC^™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher functionality packaging density, lower communication latency, and lower energy consumption per bit data. 3D packaging is challenging and requires overcoming three major challenges - thermal, power delivery, and yield. The SoIC, as industry-first 3D logic-on-logic and memory-on-logic chiplet stacking technology platform, enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies, all to be integrated in a single, compact new system chip. From external appearance, SoIC looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded. As SoIC is fabricated using "front-end" process, it can be holistically integrated into variant "back-end" advanced packaging technology platforms such as flip chip, integrated fan-out (aka InFO), 3DIC, and 2.5D with Si interposer (e.g. CoWoS^™) [1-2] to provide a miniaturized and highly integrated HI SiP for the future HPC, AI, 5G, and edge computing applications. With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 μm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions. In this paper, we demonstrated for the first time an integration of SoIC chip into InFO_PoP without increasing its form-factor. The SoIC was made on a logic-on-logic stacking to validate the design rules, process maturity, and reliability.