A 22-bit Read-Out IC With 7-ppm INL and Sub-100- \mu Hz 1/ f Corner for DC Measurement Systems

• Published in: IEEE journal of solid-state circuits 2019-11, Vol.54 (11), p.3086-3096
• Main Authors: Jun, Jaehoon, Park, Soungchul, Kang, Junho, Kim, Suhwan
• Format: Article
• Language: English
• Subjects: Bridge circuits; Choppers (circuits); Chopping technique; differential difference amplifier (DDA); energy efficiency; Energy resolution; full-on-chip integration; gain programmability; Impedance; incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC); instrumentation amplifier (IA); Integrated circuits; Low-frequency noise; read-out; Thermistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2934817

A 22-bit read-out integrated circuit (IC) is constructed from a capacitively coupled instrumentation amplifier (CCIA) followed by an incremental delta-sigma (ΔΣ) analogto-digital converter (ADC), both of which have programmable gain. The CCIA has a cascode Miller-compensated differential difference amplifier (DDA) with clamp transistors for energy efficiency. The offset and 1/f noise of the fully differential read-out IC are suppressed by chopping and correlated double sampling (CDS) techniques, which are synchronized with sampling by the ADC. Residual low-frequency noise is reduced by the second-order system-level chopping technique with an on-chip moving-averaged finite impulse response (FIR) filter. Implemented in a standard 0.13-μm CMOS process, the readout IC achieves a maximum effective resolution (ER) of 21.9 bit, an integral nonlinearity (INL) of 7 ppm, and a 1/f corner of 40 μHz. The chip draws only 142 μA from 3-V supply and 18 μA from the 1.5-V supply, and it has an active area of 0.65 mm 2 including digital filter.