Area estimation for DSP algorithms

In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. A...

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Bibliographic Details
Main Authors: Elleithy, K.M., Amin, A.A.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Analytical models
Circuits
DH-HEMTs
Digital signal processing
Lattices
Predictive models
Stochastic processes
Wire
Wiring
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Description
Summary:In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. Area estimation before final layout is important for design evaluation and for the prediction of the chip floorplan.
ISSN:1520-6130
2374-7390
DOI:10.1109/SIPS.2000.886760