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OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs
The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger-Poisson system. Our...
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creator | Long, Yuxiong Huang, Jun Z. Wei, Zhongming Luo, Jun-Wei Jiang, Xiangwei |
description | The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger-Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111). |
doi_str_mv | 10.1109/SISPAD.2019.8870452 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_8870452</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8870452</ieee_id><sourcerecordid>8870452</sourcerecordid><originalsourceid>FETCH-LOGICAL-i118t-62da7844531005b941c95988f9ac2326220eeea7feca9b1edd5b92022242d44c3</originalsourceid><addsrcrecordid>eNot0NFqwjAUBuBsMJi4PoE3eYG6nNO0SS7FrU6QKdTd7EZie9wyurYk8cI9_QoKB374-fgvDmMzEHMAYZ6rdbVbvMxRgJlrrYTM8Y4lRmlQqEcghbxnEzCySCFX6pElIfwIIQB1gUpP2Oe2LPny7D11kVfnYfAUgus7frzwlY2UfvVd9H3bUsOr6K3r-Hj7b-LvabwMNKJF4DtHfz21VEfval66rnzdhyf2cLJtoOSWU_Yx1su3dLNdrZeLTeoAdEwLbKzSUuYZCJEfjYTa5Ebrk7E1ZlggCiKy6kS1NUegphkRCkSU2EhZZ1M2u-660R0G736tvxxu38j-AaOrUr0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs</title><source>IEEE Xplore All Conference Series</source><creator>Long, Yuxiong ; Huang, Jun Z. ; Wei, Zhongming ; Luo, Jun-Wei ; Jiang, Xiangwei</creator><creatorcontrib>Long, Yuxiong ; Huang, Jun Z. ; Wei, Zhongming ; Luo, Jun-Wei ; Jiang, Xiangwei</creatorcontrib><description>The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger-Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).</description><identifier>EISSN: 1946-1577</identifier><identifier>EISBN: 9781728109404</identifier><identifier>EISBN: 172810940X</identifier><identifier>DOI: 10.1109/SISPAD.2019.8870452</identifier><language>eng</language><publisher>IEEE</publisher><subject>FinFET ; Piezoelectric ; Steep slope ; strain modulation</subject><ispartof>2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8870452$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8870452$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Long, Yuxiong</creatorcontrib><creatorcontrib>Huang, Jun Z.</creatorcontrib><creatorcontrib>Wei, Zhongming</creatorcontrib><creatorcontrib>Luo, Jun-Wei</creatorcontrib><creatorcontrib>Jiang, Xiangwei</creatorcontrib><title>OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs</title><title>2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)</title><addtitle>SISPAD</addtitle><description>The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger-Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).</description><subject>FinFET</subject><subject>Piezoelectric</subject><subject>Steep slope</subject><subject>strain modulation</subject><issn>1946-1577</issn><isbn>9781728109404</isbn><isbn>172810940X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2019</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNot0NFqwjAUBuBsMJi4PoE3eYG6nNO0SS7FrU6QKdTd7EZie9wyurYk8cI9_QoKB374-fgvDmMzEHMAYZ6rdbVbvMxRgJlrrYTM8Y4lRmlQqEcghbxnEzCySCFX6pElIfwIIQB1gUpP2Oe2LPny7D11kVfnYfAUgus7frzwlY2UfvVd9H3bUsOr6K3r-Hj7b-LvabwMNKJF4DtHfz21VEfval66rnzdhyf2cLJtoOSWU_Yx1su3dLNdrZeLTeoAdEwLbKzSUuYZCJEfjYTa5Ebrk7E1ZlggCiKy6kS1NUegphkRCkSU2EhZZ1M2u-660R0G736tvxxu38j-AaOrUr0</recordid><startdate>201909</startdate><enddate>201909</enddate><creator>Long, Yuxiong</creator><creator>Huang, Jun Z.</creator><creator>Wei, Zhongming</creator><creator>Luo, Jun-Wei</creator><creator>Jiang, Xiangwei</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201909</creationdate><title>OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs</title><author>Long, Yuxiong ; Huang, Jun Z. ; Wei, Zhongming ; Luo, Jun-Wei ; Jiang, Xiangwei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i118t-62da7844531005b941c95988f9ac2326220eeea7feca9b1edd5b92022242d44c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2019</creationdate><topic>FinFET</topic><topic>Piezoelectric</topic><topic>Steep slope</topic><topic>strain modulation</topic><toplevel>online_resources</toplevel><creatorcontrib>Long, Yuxiong</creatorcontrib><creatorcontrib>Huang, Jun Z.</creatorcontrib><creatorcontrib>Wei, Zhongming</creatorcontrib><creatorcontrib>Luo, Jun-Wei</creatorcontrib><creatorcontrib>Jiang, Xiangwei</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Long, Yuxiong</au><au>Huang, Jun Z.</au><au>Wei, Zhongming</au><au>Luo, Jun-Wei</au><au>Jiang, Xiangwei</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs</atitle><btitle>2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)</btitle><stitle>SISPAD</stitle><date>2019-09</date><risdate>2019</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><eissn>1946-1577</eissn><eisbn>9781728109404</eisbn><eisbn>172810940X</eisbn><abstract>The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger-Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).</abstract><pub>IEEE</pub><doi>10.1109/SISPAD.2019.8870452</doi><tpages>4</tpages></addata></record> |
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issn | 1946-1577 |
language | eng |
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subjects | FinFET Piezoelectric Steep slope strain modulation |
title | OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T18%3A13%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=OFF%20Current%20Suppression%20by%20Gate-gontrolled%20Strain%20in%20The%20N-type%20GaAs%20Piezoelectric%20FinFETs&rft.btitle=2019%20International%20Conference%20on%20Simulation%20of%20Semiconductor%20Processes%20and%20Devices%20(SISPAD)&rft.au=Long,%20Yuxiong&rft.date=2019-09&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.eissn=1946-1577&rft_id=info:doi/10.1109/SISPAD.2019.8870452&rft.eisbn=9781728109404&rft.eisbn_list=172810940X&rft_dat=%3Cieee_CHZPO%3E8870452%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i118t-62da7844531005b941c95988f9ac2326220eeea7feca9b1edd5b92022242d44c3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=8870452&rfr_iscdi=true |