Electromagnetic analysis of via arrays for different RF-CMOS technological nodes

• Main Authors: Sanabria, Carlos, Aranda, Monico Linares
• Format: Conference Proceeding
• Language: English
• Subjects: Electromagnetics; EM simulations; High frequency; Integrated circuit interconnections; Metals; On-Silicon vias; Resistance; RF-CMOS integrated circuits; Scattering parameters
• ISSN: 2642-3766
• DOI: 10.1109/ICEEE.2019.8884484

With the scaling trend, the newer technologies have increased the size and number of metal layers to compensate the high integration density in the design of integrated circuits (ICs). The interconnections in the CMOS process have evolved from simple geometries to complex topologies with several thickness in its metal layers, intermetallic connections (vias) with different transversal areas and groups of dielectric materials between each metal layer. The interconnections in the IC introduces parasitic elements which depends of the designed IC and its operation frequency. In this work, we focused in the analysis of via arrays parasitic elements for high frequency applications. An electromagnetic (EM) analysis in different technologies was performed by using simulated 3D models of the via arrays extracted from a full wave solver with the objective to see the performance of the via arrays under high frequency effects. The results show that by increasing the connection area in the vertical interconnections not lead to lower parasitic behavior due to the inductive characteristic present in these interconnections at high frequency ranges.