A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator

This brief presents a 2 nd -order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a lossless integrator for achieving low power and high NS efficiency. It implements the lossless integrator through a ping-pong structure and a low-gain dynamic amplifi...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2020-10, Vol.67 (10), p.1819-1823
Main Authors: Zhang, Yanbo, Liu, Shubin, Tian, Binbin, Zhu, Yan, Chan, Chi-Hang, Zhu, Zhangming
Format: Article
Language:English
Subjects:
Amplification
Amplifiers
Analog to digital conversion
Analog to digital converters
Analog-to-digital converter (ADC)
Capacitors
CMOS
dynamic amplifier
Energy conversion efficiency
Energy resolution
Figure of merit
Gain
lossless integrator
lossy integrator
Noise
Noise levels
Noise shaping
noise shaping (NS)
Oversampling
ping pong
Quantization (signal)
Registers
successive approximation register (SAR)
Timing
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Summary:This brief presents a 2 nd -order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a lossless integrator for achieving low power and high NS efficiency. It implements the lossless integrator through a ping-pong structure and a low-gain dynamic amplifier with moderate gain variation tolerance. Taking advantage of the lossless integrator, a low resolution SAR ADC is allowed under the same quantization noise budget. Fabricated in a 65-nm CMOS process, the prototype 8-bit NS-SAR ADC consumes 1.24 mW at 1.2 V while operating at 100 MS/s. It achieves a peak signal to noise and distortion ratio (SNDR) of 77 dB over a bandwidth of 3.125 MHz at the oversampling ratio (OSR) of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2019.2957727