DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip

• Main Authors: Kunthara, Rose George, Neethu, K, James, Rekha K, Sleeba, Simi Zerine, Jose, John
• Format: Conference Proceeding
• Language: English
• Subjects: buffer-less; deflection routing; flit latency; Network-on-Chip; Routing; Three-dimensional displays; Through-silicon vias; Topology; Two dimensional displays
• ISSN: 2159-3450
• DOI: 10.1109/TENCON.2019.8929475

Network on Chip (NoC) is embraced as an interconnect solution for the design of large tiled chip multiprocessors (TCMP). Bufferless NoC router is a promising approach due to its simple router design, energy and hardware efficiency. NoC, which rely on underlying network architecture, is characterized by performance measures like latency, deflection rate, throughput and power. In this paper, we come up with DoLaR architecture to raise performance of standard bufferless 2D mesh NoC by stacking two similar layers of 8×8 meshes one above the other. DoLaR employs standard 5-port bufferless router architecture and the unused ports of edge routers are utilized to make vertical interconnections between the layers. Simulation results show that our proposed design surpasses existing state-of-the-art 5-port 2D mesh and torus bufferless router designs in terms of better network saturation point and minimized deflection rate, average flit latency and power consumption.