Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan arch...

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Main Author: Whetsel, L.
Format: Conference Proceeding
Language:English
Subjects:
Batteries
Built-in self-test
Circuit testing
Computer architecture
Digital signal processing
Integrated circuit testing
Logic circuits
Logic testing
Packaging
Wafer scale integration
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creator Whetsel, L.
description Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture.
doi_str_mv 10.1109/TEST.2000.894297
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2378-2250
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source IEEE Xplore All Conference Series
subjects Batteries
Built-in self-test
Circuit testing
Computer architecture
Digital signal processing
Integrated circuit testing
Logic circuits
Logic testing
Packaging
Wafer scale integration
title Adapting scan architectures for low power operation
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