A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any loa...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2020-04, Vol.55 (4), p.977-987
Main Authors: Ahmed, Khondker Zakir, Krishnamurthy, Harish K., Augustine, Charles, Liu, Xiaosen, Weng, Sheldon, Ravichandran, Krishnan, Tschanz, James W., De, Vivek
Format: Article
Language:English
Subjects:
CMOS
computation voltage regulator
Computational digital low dropout (CDLDO)
digital LDO (DLDO)
IIR filters
LDO regulator
Mathematical model
Regulation
Regulators
Settling
Timing
Transient analysis
Transient response
Voltage control
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Summary:A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns di/dt ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2961854