The cache memory system for CalmRISC32

The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and redu...

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Bibliographic Details
Main Authors: Kil-Whan Lee, Jang-Soo Lee, Gi-Ho Park, Jung-Hoon Lee, Tack-Don Han, Shin-Dug Kim, Yong-Chun Kim, Seh-Woong Jung, Kwang-Yup Lee
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Cache memory
Computer science
Cooperative caching
Deductive databases
Embedded computing
Energy consumption
Large scale integration
Power system modeling
Spatial resolution
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Summary:The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.
DOI:10.1109/APASIC.2000.896973