TWiCe: preventing row-hammering by exploiting time window counters

• Main Authors: Lee, Eojin, Kang, Ingab, Lee, Sukhan, Suh, G. Edward, Ahn, Jung Ho
• Format: Conference Proceeding
• Language: English
• Subjects: Computer systems organization; Computer systems organization > Dependable and fault-tolerant systems and networks; Computer systems organization > Dependable and fault-tolerant systems and networks > Processors and memory architectures; Hardware; Hardware > Integrated circuits; Hardware > Integrated circuits > Semiconductor memory; Information systems; Information systems > Information storage systems; Information systems > Information storage systems > Information storage technologies; Security and privacy; Security and privacy > Security in hardware; Security and privacy > Security in hardware > Hardware attacks and countermeasures; Security and privacy > Security in hardware > Hardware attacks and countermeasures > Side-channel analysis and countermeasures; Security and privacy > Security in hardware > Tamper-proof and tamper-resistant designs; Security and privacy > Systems security
• ISSN: 2575-713X
• DOI: 10.1145/3307650.3322232

Computer systems using DRAM are exposed to row-hammer (RH) attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent RH, but they either incur large area overhead, suffer from noticeable performance drop on adversarial memory access patterns, or provide probabilistic protection with no capability to detect attacks. In this paper, we propose a new counter-based RH prevention solution named Time Window Counter (TWiCe) based row refresh, which accurately detects potential RH attacks only using a small number of counters with a minimal performance impact. We first make a key observation that the number of rows that can cause RH is limited by the maximum values of row activation frequency and DRAM cell retention time. We calculate the maximum number of required counter entries per DRAM bank, with which TWiCe prevents RH with a strong deterministic guarantee. We leverage pseudo-associative cache design and separate the TWiCe table to further reduce area and energy overheads. TWiCe incurs no performance overhead on normal DRAM operations and less than 0.7% area and energy overheads over contemporary DRAM devices. Our evaluation shows that TWiCe makes no more than 0.006% of additional DRAM row activations for adversarial memory access patterns including RH attack scenarios.