CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability

• Main Authors: Hassan, Hasan, Patel, Minesh, Kim, Jeremie S., Yaglikci, A. Giray, Vijaykumar, Nandita, Ghiasi, Nika Mansouri, Ghose, Saugata, Mutlu, Onur
• Format: Conference Proceeding
• Language: English
• Subjects: Computer systems organization; Computer systems organization > Architectures; Computer systems organization > Dependable and fault-tolerant systems and networks; Computer systems organization > Dependable and fault-tolerant systems and networks > Processors and memory architectures; DRAM; energy; Hardware; Hardware > Emerging technologies; Hardware > Emerging technologies > Memory and dense storage; Hardware > Integrated circuits; Hardware > Integrated circuits > Semiconductor memory; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory; Hardware > Integrated circuits > Semiconductor memory > Static memory; memory systems; power; reliability
• ISSN: 2575-713X
• DOI: 10.1145/3307650.3322231

DRAM has been the dominant technology for architecting main memory for decades. Recent trends in multi-core system design and large-dataset applications have amplified the role of DRAM as a critical system bottleneck. We propose Copy-Row DRAM (CROW), a flexible substrate that enables new mechanisms for improving DRAM performance, energy efficiency, and reliability. We use the CROW substrate to implement 1) a low-cost in-DRAM caching mechanism that lowers DRAM activation latency to frequently-accessed rows by 38% and 2) a mechanism that avoids the use of short-retention-time rows to mitigate the performance and energy overhead of DRAM refresh operations. CROW's flexibility allows the implementation of both mechanisms at the same time. Our evaluations show that the two mechanisms synergistically improve system performance by 20.0% and reduce DRAM energy by 22.3% for memory-intensive four-core workloads, while incurring 0.48% extra area overhead in the DRAM chip and 11.3 KiB storage overhead in the memory controller, and consuming 1.6% of DRAM storage capacity, for one particular implementation.