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OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints
OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (
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| creator | Sandrini, J. Barlas, M. Nodin, J. F. Billoint, O. Molas, G. Fournel, R. Nowak, E. Gaillard, F. Cagli, C. Grenouillet, L. Meli, V. Castellani, N. Hammad, I. Bernasconi, S. Aussenac, F. Van Duijn, S. Audoit, G. |
| description | OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes ( |
| doi_str_mv | 10.1109/IEDM19573.2019.8993484 |
| format | conference_proceeding |
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F. ; Billoint, O. ; Molas, G. ; Fournel, R. ; Nowak, E. ; Gaillard, F. ; Cagli, C. ; Grenouillet, L. ; Meli, V. ; Castellani, N. ; Hammad, I. ; Bernasconi, S. ; Aussenac, F. ; Van Duijn, S. ; Audoit, G.</creator><creatorcontrib>Sandrini, J. ; Barlas, M. ; Nodin, J. F. ; Billoint, O. ; Molas, G. ; Fournel, R. ; Nowak, E. ; Gaillard, F. ; Cagli, C. ; Grenouillet, L. ; Meli, V. ; Castellani, N. ; Hammad, I. ; Bernasconi, S. ; Aussenac, F. ; Van Duijn, S. ; Audoit, G.</creatorcontrib><description>OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (<= 40nm), thanks mainly to its low manufacturing cost. To scale the bitcell, both the OxRAM and the selector device must be taken into account. In this paper we first show how the OxRAM reliability is impacted by scaling down to 30nm in diameter, focusing on the forming voltage, BER and data retention on a large statistics (4kbit arrays). Several strategies are provided to reduce the BER leading to a projected 10 -6 BER result. We then illustrate how thin gate oxide transistors (GO1/SG) can meet the OxRAM high voltage requirement as the memory bit approaches 100nm diameter, and we demonstrate an OxRAM (120nm) co-integration with FDSOI transistors with remarkably good performance (endurance up to 10 7 cycles on single bit). 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To scale the bitcell, both the OxRAM and the selector device must be taken into account. In this paper we first show how the OxRAM reliability is impacted by scaling down to 30nm in diameter, focusing on the forming voltage, BER and data retention on a large statistics (4kbit arrays). Several strategies are provided to reduce the BER leading to a projected 10 -6 BER result. We then illustrate how thin gate oxide transistors (GO1/SG) can meet the OxRAM high voltage requirement as the memory bit approaches 100nm diameter, and we demonstrate an OxRAM (120nm) co-integration with FDSOI transistors with remarkably good performance (endurance up to 10 7 cycles on single bit). Eventually we illustrate a design example of OxRAM embedded solution in 40nm, 32Mb+ECC, featuring a 0.120µm² bitcell and a 170nm OxRAM cell.</description><issn>2156-017X</issn><isbn>1728140323</isbn><isbn>9781728140322</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2019</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkF9LwzAUxaMguE0_gSD5Aq351ybxbcxNBxsDUfBtpM3tjHRpSeJwL352q44L98A5Py6ci9AtJTmlRN8t5w9rqgvJc0aozpXWXChxhsZUMkUF4YyfoxGjRZkRKt8u0TjGD0KYLHQxQt-br-fpGjddwLCvwFqwOHbtZ3Kdj7jz2NiD8fXg-s7CPY61aZ3f4R5C7KFO7gAR1wPrLITfICaTXExu4HCA1pnKtS4dsfEWW4hu5__wFIzzKV6hi8a0Ea5POkGvi_nL7ClbbR6Xs-kqe2dcpgygaqxg0jCjmOSlsoZzWytRlVQP04iaqLKCobgSoI205bBLLRpFhISCT9DN_10HANs-uL0Jx-3pV_wHHGpiKg</recordid><startdate>201912</startdate><enddate>201912</enddate><creator>Sandrini, J.</creator><creator>Barlas, M.</creator><creator>Nodin, J. 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F. ; Billoint, O. ; Molas, G. ; Fournel, R. ; Nowak, E. ; Gaillard, F. ; Cagli, C. ; Grenouillet, L. ; Meli, V. ; Castellani, N. ; Hammad, I. ; Bernasconi, S. ; Aussenac, F. ; Van Duijn, S. ; Audoit, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-h237t-eebfd427a2a827368da33dc84b619191f4c086be48484e9a7d6e9a694f8047e53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2019</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Sandrini, J.</creatorcontrib><creatorcontrib>Barlas, M.</creatorcontrib><creatorcontrib>Nodin, J. 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F.</au><au>Billoint, O.</au><au>Molas, G.</au><au>Fournel, R.</au><au>Nowak, E.</au><au>Gaillard, F.</au><au>Cagli, C.</au><au>Grenouillet, L.</au><au>Meli, V.</au><au>Castellani, N.</au><au>Hammad, I.</au><au>Bernasconi, S.</au><au>Aussenac, F.</au><au>Van Duijn, S.</au><au>Audoit, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints</atitle><btitle>2019 IEEE International Electron Devices Meeting (IEDM)</btitle><stitle>IEDM</stitle><date>2019-12</date><risdate>2019</risdate><spage>30.5.1</spage><epage>30.5.4</epage><pages>30.5.1-30.5.4</pages><eissn>2156-017X</eissn><eisbn>1728140323</eisbn><eisbn>9781728140322</eisbn><abstract>OxRAM technology is one of the strongest candidates for embedded solutions at scaled nodes (<= 40nm), thanks mainly to its low manufacturing cost. To scale the bitcell, both the OxRAM and the selector device must be taken into account. In this paper we first show how the OxRAM reliability is impacted by scaling down to 30nm in diameter, focusing on the forming voltage, BER and data retention on a large statistics (4kbit arrays). Several strategies are provided to reduce the BER leading to a projected 10 -6 BER result. We then illustrate how thin gate oxide transistors (GO1/SG) can meet the OxRAM high voltage requirement as the memory bit approaches 100nm diameter, and we demonstrate an OxRAM (120nm) co-integration with FDSOI transistors with remarkably good performance (endurance up to 10 7 cycles on single bit). Eventually we illustrate a design example of OxRAM embedded solution in 40nm, 32Mb+ECC, featuring a 0.120µm² bitcell and a 170nm OxRAM cell.</abstract><pub>IEEE</pub><doi>10.1109/IEDM19573.2019.8993484</doi></addata></record> |
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| title | OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints |
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