Integrated Deep Trench Capacitor in Si Interposer for CoWoS Heterogeneous Integration

• Main Authors: Hou, S.Y., Wu, C.H., Yu, Douglas, Hsia, H., Tsai, C.H., Ting, K.C., Yu, T.H., Lee, Y.W., Chen, F.C., Chiou, W.C., Wang, C.T.
• Format: Conference Proceeding
• Language: English
• ISSN: 2156-017X
• DOI: 10.1109/IEDM19573.2019.8993498

To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine-pitch interconnects for chip-on-wafer-on-substrate (CoWoS) integration. A specific capacitance density (C s ) of up to 340 nF/mm 2 is achieved over a large capacitor array, providing a total capacitance (C t ) of up to 68 μF per interposer die. The HK dielectric has intrinsic time-dependent dielectric breakdown (TDDB) lifetime of > 1,000 years at an operation voltage (V cc ) of 1.35V, and a normalized leakage current (I LK ) density