Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

This paper presents the key silicon features of Intel's 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used...

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Main Authors: Ingerly, D. B., Enamul, K., Gomes, W., Jones, D., Kolluru, K. C., Kandas, A., Kim, G.-S., Ma, H., Pantuso, D., Petersburg, C.F., Phen-givoni, M., Amin, S., Pillai, A. M., Sairam, A., Shekhar, P., Sinha, P., Stover, P., Telang, A., Zell, Z., Aryasomayajula, L., Balankutty, A., Borst, D., Chandra, A., Cheemalapati, K., Cook, C. S., Criss, R.
Format: Conference Proceeding
Language:English
Online Access:Request full text
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Summary:This paper presents the key silicon features of Intel's 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used for connection to the package along with their electrical properties.
ISSN:2156-017X
DOI:10.1109/IEDM19573.2019.8993637