An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm

To better utilize artificial intelligence (AI) in the edge domain, such that it is more attractive and fruitful, the development of low-power and -resource AI devices dedicated to online learning is very important issue to be solved. We proposed new ternarized backpropagation (TBP) algorithms [1] an...

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Bibliographic Details
Main Authors: Kaneko, Tatsuya, Momose, Hiroshi, Asai, Tetsuya
Format: Conference Proceeding
Language:English
Subjects:
Backpropagation
Edge AI
FPGA
Low power
MLP
Open-innovation platform
RNN
Ternary quantization
Training
User-driven
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Summary:To better utilize artificial intelligence (AI) in the edge domain, such that it is more attractive and fruitful, the development of low-power and -resource AI devices dedicated to online learning is very important issue to be solved. We proposed new ternarized backpropagation (TBP) algorithms [1] and verified to be favorably compatible with fixed-point 16 bit backpropagation (FixedBP). In this paper, we present our implementation method of TBP on an FPGA as an accelerator for embedded microcontrollers, and evaluate the TBP on the FPGA to achieve a 15.7 % reduction of the logic elements of the FPGA, 12.3 % reduction of the registers, 90.9 % reduction of the multipliers, and 49.8 % reduction of the SRAM usage, comparing with those for the FixedBP. We verify its capabilities for training MNIST classification task with a mini-batch size of one. In addition, we demonstrate image recognition system as application example.
ISSN:2640-0472
DOI:10.1109/ReConFig48160.2019.8994795