Hardware-software codesign and parallel implementation of a Golomb ruler derivation engine

A new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are...

Full description

Saved in:
Bibliographic Details
Main Authors: Sotiriades, E., Dollas, A., Athanas, P.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Concurrent computing
Field programmable gate arrays
Hardware
Internet
Marine vehicles
Mathematics
Microcomputers
Parallel processing
Search engines
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs.
DOI:10.1109/FPGA.2000.903410