Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple...

Full description

Saved in:
Bibliographic Details
Main Authors: Busnot, Gabriel, Sassolas, Tanguy, Ventroux, Nicolas, Moy, Matthieu
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Instruments
Kernel
Monitoring
Virtual prototyping
Workstations
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 368
container_issue
container_start_page 363
container_title
container_volume
creator Busnot, Gabriel
Sassolas, Tanguy
Ventroux, Nicolas
Moy, Matthieu
description To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).
doi_str_mv 10.1109/ASP-DAC47756.2020.9045568
format conference_proceeding
fullrecord <record><control><sourceid>acm_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_9045568</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9045568</ieee_id><sourcerecordid>acm_books_10_1109_ASP_DAC47756_2020_9045568</sourcerecordid><originalsourceid>FETCH-LOGICAL-a380t-cf5ae46e08318ec600cf1a500b36f7e5525777e81a96a495fd5cfda8a57667f53</originalsourceid><addsrcrecordid>eNqVkE9LwzAYh6MiOOc-gZf6ATqTtG-SHkf9CxMHnbBbeNsmEGyb0VRh397ObeDV0-_w8PwODyF3jM4Zo9n9oljFD4s8lRLEnFNO5xlNAYQ6I9dMcsVSxhN6TiacQRKLTG4u_oIrMgvBlRQAZMppOiGbYsCuxr6Oc99uG4fdEK2wx6YxTVTswmDaPCpc-9Xg4HwXeRstvQ-m2cVr15o6WvfYBax-4dJ8j9abr00TbsilxSaY2XGn5OPpcZ2_xMv359d8sYwxUXSIKwtoUmGoSpgylaC0sgyB0jIRVhoADlJKoxhmAtMMbA2VrVEhSCGkhWRKbg-_zhijt71rsd_pY5WRqgPFqtWl959BM6r3KfWYUp9S6n3Kk6TL3hk7qvzfavIDENl1FA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models</title><source>IEEE Xplore All Conference Series</source><creator>Busnot, Gabriel ; Sassolas, Tanguy ; Ventroux, Nicolas ; Moy, Matthieu</creator><creatorcontrib>Busnot, Gabriel ; Sassolas, Tanguy ; Ventroux, Nicolas ; Moy, Matthieu</creatorcontrib><description>To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).</description><identifier>ISBN: 1728141230</identifier><identifier>ISBN: 9781728141237</identifier><identifier>EISSN: 2153-697X</identifier><identifier>EISBN: 1728141230</identifier><identifier>EISBN: 9781728141237</identifier><identifier>DOI: 10.1109/ASP-DAC47756.2020.9045568</identifier><language>eng</language><publisher>Piscataway, NJ, USA: IEEE Press</publisher><subject>Analytical models ; Instruments ; Kernel ; Monitoring ; Virtual prototyping ; Workstations</subject><ispartof>2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, p.363-368</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9045568$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,23930,23931,25140,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9045568$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Busnot, Gabriel</creatorcontrib><creatorcontrib>Sassolas, Tanguy</creatorcontrib><creatorcontrib>Ventroux, Nicolas</creatorcontrib><creatorcontrib>Moy, Matthieu</creatorcontrib><title>Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models</title><title>2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)</title><addtitle>ASP-DAC</addtitle><description>To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).</description><subject>Analytical models</subject><subject>Instruments</subject><subject>Kernel</subject><subject>Monitoring</subject><subject>Virtual prototyping</subject><subject>Workstations</subject><issn>2153-697X</issn><isbn>1728141230</isbn><isbn>9781728141237</isbn><isbn>1728141230</isbn><isbn>9781728141237</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2020</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNqVkE9LwzAYh6MiOOc-gZf6ATqTtG-SHkf9CxMHnbBbeNsmEGyb0VRh397ObeDV0-_w8PwODyF3jM4Zo9n9oljFD4s8lRLEnFNO5xlNAYQ6I9dMcsVSxhN6TiacQRKLTG4u_oIrMgvBlRQAZMppOiGbYsCuxr6Oc99uG4fdEK2wx6YxTVTswmDaPCpc-9Xg4HwXeRstvQ-m2cVr15o6WvfYBax-4dJ8j9abr00TbsilxSaY2XGn5OPpcZ2_xMv359d8sYwxUXSIKwtoUmGoSpgylaC0sgyB0jIRVhoADlJKoxhmAtMMbA2VrVEhSCGkhWRKbg-_zhijt71rsd_pY5WRqgPFqtWl959BM6r3KfWYUp9S6n3Kk6TL3hk7qvzfavIDENl1FA</recordid><startdate>20200101</startdate><enddate>20200101</enddate><creator>Busnot, Gabriel</creator><creator>Sassolas, Tanguy</creator><creator>Ventroux, Nicolas</creator><creator>Moy, Matthieu</creator><general>IEEE Press</general><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20200101</creationdate><title>Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models</title><author>Busnot, Gabriel ; Sassolas, Tanguy ; Ventroux, Nicolas ; Moy, Matthieu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a380t-cf5ae46e08318ec600cf1a500b36f7e5525777e81a96a495fd5cfda8a57667f53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Analytical models</topic><topic>Instruments</topic><topic>Kernel</topic><topic>Monitoring</topic><topic>Virtual prototyping</topic><topic>Workstations</topic><toplevel>online_resources</toplevel><creatorcontrib>Busnot, Gabriel</creatorcontrib><creatorcontrib>Sassolas, Tanguy</creatorcontrib><creatorcontrib>Ventroux, Nicolas</creatorcontrib><creatorcontrib>Moy, Matthieu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Busnot, Gabriel</au><au>Sassolas, Tanguy</au><au>Ventroux, Nicolas</au><au>Moy, Matthieu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models</atitle><btitle>2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)</btitle><stitle>ASP-DAC</stitle><date>2020-01-01</date><risdate>2020</risdate><spage>363</spage><epage>368</epage><pages>363-368</pages><eissn>2153-697X</eissn><isbn>1728141230</isbn><isbn>9781728141237</isbn><eisbn>1728141230</eisbn><eisbn>9781728141237</eisbn><abstract>To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).</abstract><cop>Piscataway, NJ, USA</cop><pub>IEEE Press</pub><doi>10.1109/ASP-DAC47756.2020.9045568</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1728141230
ispartof 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, p.363-368
issn 2153-697X
language eng
recordid cdi_ieee_primary_9045568
source IEEE Xplore All Conference Series
subjects Analytical models
Instruments
Kernel
Monitoring
Virtual prototyping
Workstations
title Standard-Compliant Parallel SystemC Simulation of Loosely-Timed Transaction Level Models
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T20%3A07%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-acm_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Standard-Compliant%20Parallel%20SystemC%20Simulation%20of%20Loosely-Timed%20Transaction%20Level%20Models&rft.btitle=2020%2025th%20Asia%20and%20South%20Pacific%20Design%20Automation%20Conference%20(ASP-DAC)&rft.au=Busnot,%20Gabriel&rft.date=2020-01-01&rft.spage=363&rft.epage=368&rft.pages=363-368&rft.eissn=2153-697X&rft.isbn=1728141230&rft.isbn_list=9781728141237&rft_id=info:doi/10.1109/ASP-DAC47756.2020.9045568&rft.eisbn=1728141230&rft.eisbn_list=9781728141237&rft_dat=%3Cacm_CHZPO%3Eacm_books_10_1109_ASP_DAC47756_2020_9045568%3C/acm_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-a380t-cf5ae46e08318ec600cf1a500b36f7e5525777e81a96a495fd5cfda8a57667f53%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=9045568&rfr_iscdi=true