Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools

Chiplet integration using 2.5D packaging is gaining popularity nowadays which enables several interesting features like heterogeneous integration and drop-in design method. In the traditional die-by-die approach of designing a 2.5D system, each chiplet is designed independently without any knowledge...

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Bibliographic Details
Main Authors: Kabir, MD Arafat, Peng, Yarui
Format: Conference Proceeding
Language:English
Subjects:
2.5D Design
Chip scale packaging
Chip-Package Co-Design
Design automation
Design methodology
Package Design
Packaging
Redistribution Layer Planning
Track Assignment
Two dimensional displays
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Summary:Chiplet integration using 2.5D packaging is gaining popularity nowadays which enables several interesting features like heterogeneous integration and drop-in design method. In the traditional die-by-die approach of designing a 2.5D system, each chiplet is designed independently without any knowledge of the package RDLs. In this paper, we propose a Chip-Package Co-Design flow for implementing 2.5D systems using existing commercial chip design tools. Our flow encompasses 2.5D-aware partitioning suitable for SoC design, Chip-Package Floorplanning, and post-design analysis and verification of the entire 2.5D system. We also designed our own package planners to route RDL layers on top of chiplet layers. We use an ARM Cortex-M0 SoC system to illustrate our flow and compare analysis results with a monolithic 2D implementation of the same system. We also compare two different 2.5D implementations of the same SoC system following the drop-in approach. Alongside the traditional die-by-die approach, our holistic flow enables design efficiency and flexibility with accurate cross-boundary parasitic extraction and design verification.
ISSN:2153-697X
DOI:10.1109/ASP-DAC47756.2020.9045734