Multi-Channel High-Resolution Pulse-Width Modulation IP-Core Implementation for FPGA and SoC Device

• Main Authors: Corna, N., Lusardi, N., Garzetti, F., Geraci, A., Gustin, M.
• Format: Conference Proceeding
• Language: English
• Subjects: ARM Advanced eXtensible Interface (ARM AXI); Delays; Digital-to-Time Converter (DTC); Field programmable gate arrays; Field-Programmable Gate Array (FPGA); Generators; Pulse width modulation; Pulse-Width Modulation (PWM); Signal resolution; System-on-Chip (SoC)
• ISSN: 2577-0829
• DOI: 10.1109/NSS/MIC42101.2019.9059801

In this contribution we present a novel implementation of a Pulse-Width Modulation (PWM) IP-Core in a Field-programmable Gate Array device (FDPGA), whose main feature is the generation of high-frequency and high-resolution Pulse-Width Modulation waves using very low amount of resources. The IP-Core is suited for any Xilinx 7-Series Field-Programmable Gate Array and System-on-Chip (SoC) and has been successfully validated on an Avnet Mini-Module Plus, which hosts a Xilinx Kintex-7 XC7K325T-1.This IP-Core reaches exceptionally high Full-Scale Ranges while keeping still a very high resolution and precision, thanks to the use of the Nutt technique. A high-frequency digital counter is used to provide a coarse part of a time wave, while the use of IDELAYE2 primitives brings down the system resolution while keeping large Full-Scale Range. Indeed, the maximum resolution on a -2/-3 speed grade device is 39 ps with precision below 16.5 ps r.m.s. over Full-Scale Range of 1.30 ms. The overall logic resources required to implement this module consist of a very low number of IDELAYE2 and other standard components, which allow the instantiation of up to 64 channels in a single Kintex-7 XC7K325T-1.The Pulse-Width Modulation IP-Core offers an ARM Advanced eXtensible Interface slave port, which allows an easy and efficient configuration both from custom programmable logic and from microprocessors, like ARM or Microblaze cores. A dual set of configuration registers is available to the user, which permits a glitch-less configuration, synchronized with the user writing on the slave port or with external events on the module I/O ports.