4-Bit Arithmetic Logic Unit That Uses Adjustable Threshold Pseudo-Dynamic Logic

• Main Authors: Agarwal, Aman, Trivedi, Avijeet Kumar, Parashar, Chirag, Pandey, Neeta
• Format: Conference Proceeding
• Language: English
• Subjects: Cadence Virtuoso; Delays; Logic gates; Power dissipation; Power-Delay Product; Pseudo-Dynamic Logic; Pseudo-Static Logic; Signal processing; Threshold voltage; Topology; Transistors; Tunable threshold
• ISSN: 2688-769X
• DOI: 10.1109/SPIN48934.2020.9071089

In this paper, in order to improve the performance and power dissipation of a chip, we present an Arithmetic and Logic Unit (ALU) using the "Power-performance tunable Pseudo-Dynamic topology". To achieve this, we have designed basic logic gates such as AND, OR and XOR. The general idea of the logic was inspired from the pseudo-dynamic logic [1]. The input and output of this logic are compatible with static gates and can replace them with pseudo-dynamic gates. The pulse generation in the intermediate nodes decreases the power dissipation. This logic uses skewing supply voltage to tune the threshold voltage which provides performance and power dissipation controllability. Although owing to the larger number of transistors used for the same functionality, pseudo-dynamic topology acquires a larger footprint as compared to static CMOS topology, but its delay and overall power dissipation is certainly better than Static CMOS logic.For carrying out our simulations and transient analysis, we used Cadence® Virtuoso® Schematic Editor and ADEL Simulator.