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Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip
A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic c...
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| creator | Shin, Taein Son, Kyungjune Kim, Seongguk Cho, Kyungjun Park, Shinyoung Kim, Subin Park, Gapyeol Sim, Boogyo Kim, Joungho |
| description | A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic components from its dense interconnection can affect the electrical performance of noise-sensitive analog-computing and small read voltage margin of the memristor. In this paper, we designed a large-scale memristor crossbar array, and modeled it into equivalent circuit models and analyzed its signal integrity considering IR drop, crosstalk and ripple. These factors were compared depending on the physical dimension of on-chip interconnection and operating frequency. Based on the eye-diagram simulation, we could successfully demonstrate the voltage margin and timing margin for memristor operations. |
| doi_str_mv | 10.1109/EPEPS47316.2019.193227 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_9073136</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9073136</ieee_id><sourcerecordid>9073136</sourcerecordid><originalsourceid>FETCH-LOGICAL-i203t-ffdcb0cf85d54ac028ce7068a92459f5e9869a55b6fa7b533620b209e142e9ab3</originalsourceid><addsrcrecordid>eNotkN9KwzAYxaMgOOaeQJC8QGf-NGlyOcrUwXSD6fX4mn1x0bYpaUV2t0d3U69-cM7hHDiE3HE25ZzZ-_l6vt7kheR6Khi3U26lEMUFmdjC8EIYniuj5CUZCa5VlnOursmk7z8YY5IbY6wekeOi6cANNHq6arNyHzq6aAdMLrYtuiHEloaWAl1Cesds46BG-oxNCv0QEy1T7PsKEp2lBAfqT9ILfiWoTxi-Y_qkM-ewxgTnNLS7Xzs2MXX74Oh57oZceah7nPxzTN4e5q_lU7ZcPS7K2TILgskh837nKua8UTuVg2PCOCyYNmBFrqxXaI22oFSlPRSVklILVglmkecCLVRyTG7_egMibrsUGkiHrWWn-6SWP1gsYnI</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip</title><source>IEEE Xplore All Conference Series</source><creator>Shin, Taein ; Son, Kyungjune ; Kim, Seongguk ; Cho, Kyungjun ; Park, Shinyoung ; Kim, Subin ; Park, Gapyeol ; Sim, Boogyo ; Kim, Joungho</creator><creatorcontrib>Shin, Taein ; Son, Kyungjune ; Kim, Seongguk ; Cho, Kyungjun ; Park, Shinyoung ; Kim, Subin ; Park, Gapyeol ; Sim, Boogyo ; Kim, Joungho</creatorcontrib><description>A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic components from its dense interconnection can affect the electrical performance of noise-sensitive analog-computing and small read voltage margin of the memristor. In this paper, we designed a large-scale memristor crossbar array, and modeled it into equivalent circuit models and analyzed its signal integrity considering IR drop, crosstalk and ripple. These factors were compared depending on the physical dimension of on-chip interconnection and operating frequency. Based on the eye-diagram simulation, we could successfully demonstrate the voltage margin and timing margin for memristor operations.</description><identifier>EISSN: 2165-4115</identifier><identifier>EISBN: 9781728145853</identifier><identifier>EISBN: 1728145856</identifier><identifier>DOI: 10.1109/EPEPS47316.2019.193227</identifier><language>eng</language><publisher>IEEE</publisher><subject>Eye-diagram ; Memristor crossbar array ; On-chip interconnection ; Signal integrity</subject><ispartof>2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2019, p.1-3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9073136$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9073136$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shin, Taein</creatorcontrib><creatorcontrib>Son, Kyungjune</creatorcontrib><creatorcontrib>Kim, Seongguk</creatorcontrib><creatorcontrib>Cho, Kyungjun</creatorcontrib><creatorcontrib>Park, Shinyoung</creatorcontrib><creatorcontrib>Kim, Subin</creatorcontrib><creatorcontrib>Park, Gapyeol</creatorcontrib><creatorcontrib>Sim, Boogyo</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><title>Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip</title><title>2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)</title><addtitle>EPEPS</addtitle><description>A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic components from its dense interconnection can affect the electrical performance of noise-sensitive analog-computing and small read voltage margin of the memristor. In this paper, we designed a large-scale memristor crossbar array, and modeled it into equivalent circuit models and analyzed its signal integrity considering IR drop, crosstalk and ripple. These factors were compared depending on the physical dimension of on-chip interconnection and operating frequency. Based on the eye-diagram simulation, we could successfully demonstrate the voltage margin and timing margin for memristor operations.</description><subject>Eye-diagram</subject><subject>Memristor crossbar array</subject><subject>On-chip interconnection</subject><subject>Signal integrity</subject><issn>2165-4115</issn><isbn>9781728145853</isbn><isbn>1728145856</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2019</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkN9KwzAYxaMgOOaeQJC8QGf-NGlyOcrUwXSD6fX4mn1x0bYpaUV2t0d3U69-cM7hHDiE3HE25ZzZ-_l6vt7kheR6Khi3U26lEMUFmdjC8EIYniuj5CUZCa5VlnOursmk7z8YY5IbY6wekeOi6cANNHq6arNyHzq6aAdMLrYtuiHEloaWAl1Cesds46BG-oxNCv0QEy1T7PsKEp2lBAfqT9ILfiWoTxi-Y_qkM-ewxgTnNLS7Xzs2MXX74Oh57oZceah7nPxzTN4e5q_lU7ZcPS7K2TILgskh837nKua8UTuVg2PCOCyYNmBFrqxXaI22oFSlPRSVklILVglmkecCLVRyTG7_egMibrsUGkiHrWWn-6SWP1gsYnI</recordid><startdate>201910</startdate><enddate>201910</enddate><creator>Shin, Taein</creator><creator>Son, Kyungjune</creator><creator>Kim, Seongguk</creator><creator>Cho, Kyungjun</creator><creator>Park, Shinyoung</creator><creator>Kim, Subin</creator><creator>Park, Gapyeol</creator><creator>Sim, Boogyo</creator><creator>Kim, Joungho</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201910</creationdate><title>Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip</title><author>Shin, Taein ; Son, Kyungjune ; Kim, Seongguk ; Cho, Kyungjun ; Park, Shinyoung ; Kim, Subin ; Park, Gapyeol ; Sim, Boogyo ; Kim, Joungho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-ffdcb0cf85d54ac028ce7068a92459f5e9869a55b6fa7b533620b209e142e9ab3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Eye-diagram</topic><topic>Memristor crossbar array</topic><topic>On-chip interconnection</topic><topic>Signal integrity</topic><toplevel>online_resources</toplevel><creatorcontrib>Shin, Taein</creatorcontrib><creatorcontrib>Son, Kyungjune</creatorcontrib><creatorcontrib>Kim, Seongguk</creatorcontrib><creatorcontrib>Cho, Kyungjun</creatorcontrib><creatorcontrib>Park, Shinyoung</creatorcontrib><creatorcontrib>Kim, Subin</creatorcontrib><creatorcontrib>Park, Gapyeol</creatorcontrib><creatorcontrib>Sim, Boogyo</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shin, Taein</au><au>Son, Kyungjune</au><au>Kim, Seongguk</au><au>Cho, Kyungjun</au><au>Park, Shinyoung</au><au>Kim, Subin</au><au>Park, Gapyeol</au><au>Sim, Boogyo</au><au>Kim, Joungho</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip</atitle><btitle>2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)</btitle><stitle>EPEPS</stitle><date>2019-10</date><risdate>2019</risdate><spage>1</spage><epage>3</epage><pages>1-3</pages><eissn>2165-4115</eissn><eisbn>9781728145853</eisbn><eisbn>1728145856</eisbn><abstract>A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic components from its dense interconnection can affect the electrical performance of noise-sensitive analog-computing and small read voltage margin of the memristor. In this paper, we designed a large-scale memristor crossbar array, and modeled it into equivalent circuit models and analyzed its signal integrity considering IR drop, crosstalk and ripple. These factors were compared depending on the physical dimension of on-chip interconnection and operating frequency. Based on the eye-diagram simulation, we could successfully demonstrate the voltage margin and timing margin for memristor operations.</abstract><pub>IEEE</pub><doi>10.1109/EPEPS47316.2019.193227</doi><tpages>3</tpages></addata></record> |
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| identifier | EISSN: 2165-4115 |
| ispartof | 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2019, p.1-3 |
| issn | 2165-4115 |
| language | eng |
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| source | IEEE Xplore All Conference Series |
| subjects | Eye-diagram Memristor crossbar array On-chip interconnection Signal integrity |
| title | Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T19%3A10%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Impact%20of%20On-Chip%20Interconnection%20in%20a%20Large-Scale%20Memristor%20Crossbar%20Array%20for%20Neural%20Network%20Accelerator%20and%20Neuromorphic%20Chip&rft.btitle=2019%20IEEE%2028th%20Conference%20on%20Electrical%20Performance%20of%20Electronic%20Packaging%20and%20Systems%20(EPEPS)&rft.au=Shin,%20Taein&rft.date=2019-10&rft.spage=1&rft.epage=3&rft.pages=1-3&rft.eissn=2165-4115&rft_id=info:doi/10.1109/EPEPS47316.2019.193227&rft.eisbn=9781728145853&rft.eisbn_list=1728145856&rft_dat=%3Cieee_CHZPO%3E9073136%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i203t-ffdcb0cf85d54ac028ce7068a92459f5e9869a55b6fa7b533620b209e142e9ab3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=9073136&rfr_iscdi=true |