A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol

This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating...

Full description

Saved in:
Bibliographic Details
Main Authors: Bichan, Mike, Ting, Clifford, Zand, Bahram, Wang, Jing, Shulyzki, Ruslana, Guthrie, James, Tyshchenko, Katya, Zhao, Junhong, Parsafar, Alireza, Liu, Eric, Vatankhahghadim, Aynaz, Sharifian, Shaham, Tyshchenko, Aleksey, De Vita, Michael, Rubab, Syed, Iyer, Sitaraman, Spagna, Fulvio, Dolev, Noam
Format: Conference Proceeding
Language:English
Subjects:
10nm
Capacitors
Clocks
Decision feedback equalizers
Jitter
NRZ
PCIe
Phase locked loops
SerDes
Temperature measurement
Transmitters
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1-32 Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology.
ISSN:2152-3630
DOI:10.1109/CICC48029.2020.9075947