A test pattern generation unit for memory NPSF built-in self test

In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for me...

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Bibliographic Details
Main Authors: Chrisanthopoulos, A., Kamoulakos, G., Tsiatouhas, Y., Arpoyanni, A.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Built-in self-test
Circuit faults
Circuit testing
Informatics
Life estimation
Signal processing
Silicon
System testing
Test pattern generators
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Description
Summary:In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for memory Type-1 NPSF testing.
DOI:10.1109/ICECS.2000.911571