SiGe BiCMOS broadband phase-aligner circuit from 1 Gb/s to 11 Gb/s

The circuit is implemented as the interface between two BiCMOS chips for the TX frontend in second- and third-generation basestations. No clock recovery is necessary in these applications. The first chip translates the incoming IQ-data stream from the baseband into a serial output data stream with a...

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Bibliographic Details
Main Authors: Hofmann, R., Jelonnek, B., Kling, H., Splett, A., Koenig, E.
Format: Conference Proceeding
Language:English
Subjects:
BiCMOS integrated circuits
Clocks
CMOS technology
Counting circuits
Delay
Germanium silicon alloys
Integrated circuit technology
Logic arrays
Silicon germanium
Switching circuits
Online Access:Request full text
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Description
Summary:The circuit is implemented as the interface between two BiCMOS chips for the TX frontend in second- and third-generation basestations. No clock recovery is necessary in these applications. The first chip translates the incoming IQ-data stream from the baseband into a serial output data stream with a bit rate up to 8.5Gb/s for CDMA-, GSM- and EDGE applications in the 2GHz range. This data stream already contains the antenna signal. To achieve this functionality, the first chip includes digital filters, interpolating stages and a /spl Sigma//spl Delta/ modulator. The second chip with input stage consisting of the presented phase-aligner circuit is a digital to analog converter (DAC).
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2001.912702