Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution

• Main Authors: Lo, Chieh Roger, Yeh, Teng-Hao, Chen, Wei-Chen, Lue, Hang-Ting, Wang, Keh-Chung, Lu, Chih-Yuan, Chang, Yao-Wen, Chen, Yung-Hsiang, Liu, Chu-Yung
• Format: Conference Proceeding
• Language: English
• Subjects: depletion mode MOSFET; Electric breakdown; Layout; Logic gates; MOSFET; Semiconductor device measurement; source/drainoffset layout; Tunneling; Voltage measurement; walk-out/walk-in effect; Word-line drive of NAND Flash
• ISSN: 1938-1891
• DOI: 10.1109/IRPS45951.2020.9129216

In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest voltage (>30V) during NAND Flash programming. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BV DSS ) from virgin state is usually lower than that after stress, which is called the "walk-out" effect. The walk-out effect can be recovered by a high-temperature baking, indicating it's not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BV DSS with acceptable transistor performances.