Reflection-Based Short Pulse Generation in CMOS

In this letter, a low cost, compact, and systematic method for generating a short pulse and efficiently delivering it to low impedance loads is proposed. The load can be a resistive on-chip or off-chip load, an antenna, or another stage such as a power combiner. The technique is inspired by time-dom...

Full description

Saved in:
Bibliographic Details
Published in:IEEE solid-state circuits letters 2020, Vol.3, p.318-321
Main Authors: Khoeini, Farzad, Hadidian, Bahareh, Zhang, Keshu, Afshari, Ehsan
Format: Article
Language:English
Subjects:
Chip formation
CMOS
Impedance
Load
Logic gates
Low cost
Power combiners
Power transmission lines
Pulse generation
Pulse measurements
reflection
Reflectometry
Semiconductor device measurement
short pulse
short-circuited termination
Transistors
transmission line
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this letter, a low cost, compact, and systematic method for generating a short pulse and efficiently delivering it to low impedance loads is proposed. The load can be a resistive on-chip or off-chip load, an antenna, or another stage such as a power combiner. The technique is inspired by time-domain reflectometry from a short-circuited termination. The technique is fully compatible with the CMOS technology. To show the feasibility of the idea, two chips are fabricated and tested in a low cost 0.11- \mu \text{m} CMOS process with f T ≈ 80GHz. The full-width at half maximum (FWHM) of the pulses are 6.8ps and 8.8ps, and the amplitudes over a 50 {\Omega } load are 0.62V and 1V. Either of the chips occupies {1160\times 540\,{\mu \mathrm {m}}^{2}} in area.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2020.3018129