Partial-response maximum-likelihood core development for a CD/DVD controller integrated circuit

A new PRML architecture is presented to demonstrate its superiority over the conventional analog channel in a DVD system. In this new architecture, the robustness to the baseline disturbance in the readback signal is emphasized in developing the algorithms for the PLL, digital gain control, asymmetr...

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Bibliographic Details
Published in:IEEE transactions on magnetics 2001-03, Vol.37 (2), p.663-669
Main Authors: Sonu, G., Nadershahi, N., Radzewicz, S., Young-Mook Kim, Jae-Wook Lee, Daeyun Shim, Cho, K.O., Hyucheol Park, Kiwon Lee, Hyun-Soo Park, Jae-Seong Shim
Format: Article
Language:English
Subjects:
Algorithms
Applied sciences
Architecture
Asymmetry
CMOS technology
Detectors
Digital
Electronics
Exact sciences and technology
Gain control
Magnetic devices
Magnetism
Mathematical models
Maximum likelihood detection
Microprocessors
Other magnetic recording and storage devices (including tapes, disks, and drums)
Phase locked loops
Programmable control
Robust control
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal processing
Viterbi algorithm
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Summary:A new PRML architecture is presented to demonstrate its superiority over the conventional analog channel in a DVD system. In this new architecture, the robustness to the baseline disturbance in the readback signal is emphasized in developing the algorithms for the PLL, digital gain control, asymmetry control, adaptive FIR filter, and Viterbi detector and post processor. In addition, a method of modeling the asymmetrical readback signal is discussed. A new algorithm for the digital PLL is described which does not require the oversampling. A simple method is presented to reduce the asymmetry in the ADC samples. To further improve the sensitivity to the baseline wandering, a Viterbi detector is designed using the difference metric approach and followed by a post processor, which corrects the baseline related errors from the VD. A test chip is fabricated using 0.35 /spl mu/m CMOS technology to demonstrate the performance of the proposed architecture.
ISSN:0018-9464
1941-0069
DOI:10.1109/20.917598