Leveraging QDI Robustness to Simplify the Design of IoT Circuits

Internet of Things devices require innovative power efficient design techniques that ensure correct operation in harsh environments, where using synchronous design can be challenging. The timing sign-off of synchronous circuits requires analysis and optimisation under multiple corners and operating...

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Bibliographic Details
Main Authors: Sartori, Marcos L. L., Wuerdig, Rodrigo N., Moreira, Matheus T., Bampi, Sergio, Calazans, Ney L. V.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous circuits
Clocks
Libraries
Logic gates
Protocols
Timing
Online Access:Request full text
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Summary:Internet of Things devices require innovative power efficient design techniques that ensure correct operation in harsh environments, where using synchronous design can be challenging. The timing sign-off of synchronous circuits requires analysis and optimisation under multiple corners and operating modes. Considering that energy efficient circuits demand dynamic voltage ranges and harsh environments impose significant variations, design sign-off may become prohibitively expensive. An alternative is quasi-delay-insensitive asynchronous design, which presents robustness against timing variations, simplifying timing sign-off. This paper leverages recent developments in asynchronous circuits design automation to achieve higher degrees of energy efficiency using voltage scaling, while ensuring solid robustness to variability.
ISSN:2158-1525
2158-1525
DOI:10.1109/ISCAS45731.2020.9181139