Low Temperature SoIC Bonding and Stacking Technology for 12-/16-Hi High Bandwidth Memory (HBM)

• Published in: IEEE transactions on electron devices 2020-12, Vol.67 (12), p.5343-5348
• Main Authors: Chen, M. F., Tsai, C. H., Ku, Terry, Chiou, W. C., Wang, C. T., Yu, Douglas
• Format: Article
• Language: English
• Subjects: 3DIC; Bandwidth; Bandwidths; Bonding; Dynamic random access memory; dynamic random access memory (DRAM); high bandwidth memory (HBM); Integrated circuits; Interconnections; Low temperature; Moore’s law; Power efficiency; Random access memory; Resistance; Stacking; Static random access memory; static random access memory (SRAM); system scaling; system-on-integrated-chip (SoIC); Temperature measurement; Through-silicon vias; wafer level system integration (WLSI)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3021358

A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is proposed and implemented for 3-D memory integration, such as 3-D static random access memory (SRAM) or dynamic random access memory (DRAM) cube. It extends not only 2-D pin count to 12000/mm 2 but also overcomes the obstacle of the stacking height. 4-Hi, 8-Hi, and 12-Hi stacks, each with 1 base die and 4, 8, and 12 dies, respectively, are realized and demonstrated in this article. The daisy chains in the 4-Hi/8-Hi/12-Hi structures incorporating over 10 000 through silicon vias (TSVs) and bonds are tested with liner {I}-{V} curves, which indicates the good bonding and stacking quality. The electrical link from base controller to top DRAM for 12-Hi and 16-Hi high bandwidth memory (HBM) structure is built up to study the bandwidth (BW) and power efficiency. Compared to \mu bump technology, the BW for the 12-Hi and 16-Hi structures using SoIC bonding shows the improvement of 18% and 20%, respectively, under same pin pitch and the power efficiency has the improvement of 8% and 15%. For thermal performance, the 12-Hi and 16-Hi SoIC-bond structure is 7% and 8% better than those using \mu bump technology, respectively. With this innovative SoIC bonding and stacking technology, the bond pitch is scalable to sub-micrometer and the die thickness is manageable to be thinner, which are prospected for the application of higher BW 3-D memory with tera byte (TB)/s per stack.