Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting

• Published in: IEEE journal of solid-state circuits 2020-12, Vol.55 (12), p.3308-3321
• Main Authors: Nagulu, Aravind, Chen, Tingjun, Zussman, Gil, Krishnaswamy, Harish
• Format: Article
• Language: English
• Subjects: Capacitors; Circuits; Circulators; Clocks; CMOS; Duplexers; Ferrite circulators; full-duplex (FD); gyrators; Inductors; Insertion loss; isolators; linear periodically time-varying (LPTV) circuits; Modulation; non-reciprocity; Power consumption; Power demand; radars; Stress concentration; Switches; Transistors; Transmission lines
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3022813

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD). This article introduces three innovations: 1) a new switched-capacitor clock-boosting scheme; 2) high-Bragg-frequency quasi-distributed transmission lines based on periodically loaded inductors; and 3) a new gyrator based on switched partially reflecting t-lines-which enable significant performance improvement for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1-GHz 180-nm SOI CMOS circulator that exhibits 2.1-/2.6-dB TX-ANT/ANT-RX IL (0.3 dB better than prior art), +34-dBm TX-ANT P1 dB (2.5 \times or 4 dB better), and 40% lower chip area, all at 39-mW power consumption (4.4 \times lower).