Intra-node high-performance computing network architecture with nanosecond-scale photonic switches [Invited]

• Published in: Journal of optical communications and networking 2020-12, Vol.12 (12), p.367-377
• Main Authors: Maniotis, Pavlos, Dupuis, Nicolas, Schares, Laurent, Kuchta, Daniel M., Taubenblatt, Marc A., Lee, Benjamin G.
• Format: Article
• Language: English
• Subjects: Accelerators; Buffers; Completion time; Computer architecture; Computer simulation; Discrete event systems; ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATION; Energy conversion efficiency; GENERAL AND MISCELLANEOUS; Graphics processing units; Network latency; Nodes; Optical buffering; Optical fiber networks; Optical switches; Optoelectronics; Photonics; Reconfiguration; Servers; Switches; Switching
• ISSN: 1943-0620; 1943-0639
• DOI: 10.1364/JOCN.399925

We propose a single-stage network architecture for intra-node connectivity that makes use of nanosecond-scale photonic switches. Although buffering at the switch points is of vital importance for complex multistage networks, this is not the case for smaller-scale single-stage networks where the end nodes are located only one hop apart. By limiting the buffering to the end points, the proposed architecture manages to minimize the required electro-optic and opto-electronic conversions, leading in this way to both low end-to-end latency and better energy efficiency. Combining these advantages with nanosecond-scale switching times can allow for high-throughput operation, even for frequent switch reconfigurations. The performance of the proposed architecture is evaluated via discrete-event simulations for a wide range of synthetic-traffic cases. The simulation results show that high-throughput operation of \ge {90}\%≥90% can be achieved even for small message sizes, i.e., 32 KB for all-to-all communication and 2 KB for uniform random traffic, at a data rate of 400 Gb/s and a switch reconfiguration time of \le {72}\;{\rm ns}≤72ns. Moreover, if 100 ns reconfiguration times are achievable as opposed to 150 ns, then for the all-to-all traffic case a 16% and 28% reduction in completion time can be achieved for message sizes of 8 KB and 1 KB, respectively. In a forthcoming era of optically interfaced processors and accelerators, nanosecond-scale photonic switches appear as a highly promising solution for keeping up with the intra-node bandwidth scaling due to their high-bandwidth, low-latency, and fast-switching capabilities.