Performance predictions for speculative, synchronous, VLSI logic simulation

VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in...

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Bibliographic Details
Published in:Proceedings. 34th Annual Simulation Symposium 2001, p.56-64
Main Authors: Noble, B.L., Wade, J.C., Chamberlain, R.D.
Format: Article
Language:English
Subjects:
Application specific integrated circuits
Circuit simulation
Computational modeling
Computer simulation
Discrete event simulation
Error correction
Hardware design languages
Logic
Predictive models
Very large scale integration
Online Access:Request full text
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Summary:VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems.
ISSN:1080-241X
0272-4715
2331-107X
DOI:10.1109/SIMSYM.2001.922115