FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose...

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Bibliographic Details
Main Authors: Shrivastava, Shashwat, Choudhury, Ziaul, Khandelwal, Shashwat, Purini, Suresh
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
FPGA
Image resolution
Parallel processing
Semi-Global Matching
stereo vision
Streaming media
Throughput
Time-frequency analysis
Transforms
Online Access:Request full text
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Summary:In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. This establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.
ISSN:1946-1488
DOI:10.1109/FPL50879.2020.00057