STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions

• Published in: IEEE journal of solid-state circuits 2021-01, Vol.56 (1), p.165-178
• Main Authors: Yamamoto, Kasho, Kawamura, Kazushi, Ando, Kota, Mertig, Normann, Takemoto, Takashi, Yamaoka, Masanao, Teramoto, Hiroshi, Sakai, Akira, Takamaeda-Yamazaki, Shinya, Motomura, Masato
• Format: Article
• Language: English
• Subjects: Annealing; Annealing processor; Automata; Cellular automata; CMOS; CMOS-based annealing chip; Combinatorial analysis; combinatorial optimization; Computer architecture; fully connected Ising model; Graphical representations; Graphs; Microprocessors; Optimization; Principal component analysis; processor architecture; Stationary state; Stochastic processes
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3027702

This article presents a high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems represented by fully connected graphs. Supporting fully connected graphs is strongly required for dealing with realistic optimization problems. Unlike previous annealing processors that follow Glauber dynamics, our proposed annealer can update multiple states of fully connected spins simultaneously by introducing different dynamics called stochastic cellular automata annealing. It allows us to utilize the pipeline-level and memory-bank-level parallelization in addition to the PE-level parallelization originally adopted in the previous annealers. The STATICA prototype chip, which supports 512-spin fully connected graph, has been fabricated with the 65-nm CMOS technology and realized as a 3 mm \times \,\,{4} mm chip. Using the fabricated 512-spin chip and numerical projections for a 2048-spin chip, we have conducted experiments to reveal the annealing performance of STATICA and examined how to control its annealing process efficiently.