A Voting Approach for Adaptive Network-on-Chip Power-Gating

• Published in: IEEE transactions on computers 2021-11, Vol.70 (11), p.1962-1975
• Main Authors: Huang, Jiayi, Bhosekar, Shilpa, Boyapati, Rahul, Wang, Ningyuan, Hur, Byul, Yum, Ki Hwan, Kim, Eun Jung
• Format: Article
• Language: English
• Subjects: Algorithms; Benchmarks; Computer architecture; Heuristic algorithms; Microarchitecture; Network interfaces; Network latency; Networks-on-chip; Power consumption; Power demand; power-gating; Routers; Routing; routing algorithm; Routing protocols; System on chip; Voting; Weight reduction; Workload; Workloads
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2020.3033163

Scalable Networks-on-Chip (NoCs) have become the standard interconnection mechanisms in large-scale multicore architectures. These NoCs consume a large fraction of the on-chip power budget, where the static portion is becoming dominant as technology scales down to sub-10nm node. Therefore, it is essential to reduce static power so as to achieve power- and energy-efficient computing. Power-Gating as an effective static power saving technique can be used to power off inactive routers for static power saving. However, packet deliveries in irregular power-gated networks suffer from detour or waiting time overhead to either route around or wake up power-gated routers. In this article, we propose Fly-Over ( Flov ) , a voting approach for dynamic router power-gating in a light-weight and distributed manner, which includes Flov router microarchitecture, adaptive power-gating policy, and low-latency dynamic routing algorithms. We evaluate Flov using synthetic workloads as well as real workloads from PARSEC 2.1 benchmark suite. Our full-system evaluations show that Flov reduces the power consumption of NoC by 31 and 20 percent, respectively, on average across several benchmarks, compared to the baseline and the state-of-the-art while maintaining the similar performance.