MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

• Main Authors: Li, Yih-Lang, Lin, Shih-Ting, Nishizawa, Shinichi, Onodera, Hidetoshi
• Format: Conference Proceeding
• Language: English
• Subjects: Boolean functions; flip-flops; inter-row connections; intra-row connections; Layout; legal routing result; Libraries; logic design; MAX-SAT based detailed router; multibit flip-flop cells; multirow cell layout synthesis; multirow cell layouts; multirow cell structure; multirow cells; multirow transistor placement algorithm; network routing; Optimization; Pins; previous cell library synthesis researches; previous SAT-based detailed router; primitive design rules; resource constrained MAX-SAT; Routing; routing flow; single-row cell library; state-of-the-art cell library; synthesized cells; Transistors; Wires
• ISSN: 1558-2434
• DOI: 10.1145/302.3415612

Multi-row cell structure has become popular for modern designs, especially for the multi-bit flip-flop (MBFF) cells, but has not been under full investigation in previous cell library synthesis researches. In this work, we propose an entire placement and routing flow for synthesizing multi-row cell layouts. The proposed new A*-based multi-row transistor placement algorithm can optimize the intra-row and inter-row connections. We also present the first MAX-SAT based detailed router to optimize the crossrow connections that also conform to primitive design rules, but not only to obtain a legal routing result in previous SAT-based detailed router. Experimental results show that the quality of synthesized cells is similar to that of a state-of-the-art cell library in [6], and better aspect ratios of multi-row cells also offer more flexible capability in assembling block designs under some aspect ratio constraints as compared to single-row cell library.