Bias Temperature Instability of GaN Cascode Power Switch

• Main Authors: Elangovan, Surya, Huang, Chun-Han, Chen, Ching-An, Chcng, Stone, Chang, Edward Yi
• Format: Conference Proceeding
• Language: English
• Subjects: Bias Temperature Instability; Degradation; Electron traps; Gallium nitride; GaN cascode power switch; Logic gates; shift and degradation; Stress; Switches; Threshold voltage
• ISSN: 1946-1550
• DOI: 10.1109/IPFA49335.2020.9260908

We present an extensive study of bias temperature instability (BTI) in Gallium Nitride (\mathrm{GaN}) MIS-HEMT based cascode power switch under positive and negative gate bias stress. We investigated the device parameter instabilities such as threshold voltage (\mathrm{V}_{\mathrm{TH}}) shift, transconductance maximum (\mathrm{G}_{\mathrm{m},\ \max}) degradation and also device turn-on or rise-time delay (\mathrm{t}_{\mathrm{R}}) . As voltage magnitude, temperature and stress time duration increases, the \mathrm{V}_{\mathrm{TH}} shift, \mathrm{G}_{\mathrm{m},\ \max} degradation and (\mathrm{t}_{\mathrm{R}}) delay continuously increases. Under positive gate bias stress, electron trapping on preexisting oxide traps causes positive \mathrm{V}_{\mathrm{TH}} shifts and \mathrm{G}_{\mathrm{m},\max} degradation. For negative gate bias stress, the field induced electron trapping on \mathrm{GaN} channel from preexisting oxide traps plays a major role on negative \mathrm{V}_{\mathrm{TH}} shifts, \mathrm{G}_{\mathrm{m}} degradation and also causes delay in rise time of the device. For the harsh positive and negative gate stress, the generation of interface traps leads the devices to larger and permanent \mathrm{V}_{\mathrm{TH}} shifts and large \mathrm{G}_{\mathrm{m},\max} degradation. The major issues are based on the presence of electronic traps in \mathrm{GaN} cascode power switch, which limits in performance, stability and lifetime continuously.