A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2021-02, Vol.68 (2), p.692-703
• Main Authors: Shiba, Kota, Omori, Tatsuo, Ueyoshi, Kodai, Takamaeda-Yamazaki, Shinya, Motomura, Masato, Hamada, Mototsugu, Kuroda, Tadahiro
• Format: Article
• Language: English
• Subjects: 3D integration; 3D memory architecture; CMOS; Coils; Couplings; deep neural networks (DNNs); Energy consumption; Inductive coupling; Metal oxide semiconductors; Power consumption; Power distribution; Random access memory; Static random access memory; static random access memory (SRAM); Three-dimensional displays; through silicon via (TSV); Through-silicon vias; ThruChip interface (TCI); Transmitters; Wireless communication
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.3037892

A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces the power of the link by 35% with a 0.4-V power supply. The SRAM utilizes an inverted bit insertion scheme that compensates for the degradation of the first transmitted bit, a coil termination scheme that aims to eliminate the ringing of 3D inductive coupling bus, and a 12:1 SerDes that minimizes power consumption and area overhead in inductive coupling channels. Low-power, large-capacity, 3-cycle latency 3D-stacked SRAM for a DNN accelerator is achieved with the combination of these techniques to serve as a replacement of 3D-stacked DRAM. The performance of the proposed 3D-SRAM is compared with HBM DRAM and achieves more than 50% lower energy consumption. The scaling scenario of the SRAM module is discussed in light of the scaling of the inductive coupling technology and logic process.