A comparison of large I/O flip chip and wire bonded packages

As many of the large ASICs integrate high speed I/O macro-cells, there is increasing interest in the electrical performance of high ball count packages. The wire bond interconnects, plating bars and package structures have come under close scrutiny as it has become paramount to improve the performan...

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Bibliographic Details
Main Authors: Bulumulla, S.B., Caggiano, M.F., Lischner, D.J., Wolf, R.K.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Bars
Bonding
Costs
Flip chip
Integrated circuit interconnections
Integrated circuit packaging
Radio frequency
Semiconductor device measurement
Wire
Online Access:Request full text
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Description
Summary:As many of the large ASICs integrate high speed I/O macro-cells, there is increasing interest in the electrical performance of high ball count packages. The wire bond interconnects, plating bars and package structures have come under close scrutiny as it has become paramount to improve the performance of large packages to meet system requirements. This work presents measured data on high ball count wire bond and flip chip packages and compares the performance of both types of packages. The results show the bandwidth limitation of the wire bond packages as well as the performance differences between different types of flip chip packages.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2001.927965