Speculative Barriers With Transactional Memory

• Published in: IEEE transactions on computers 2022-01, Vol.71 (1), p.197-208
• Main Authors: Pedrero, Manuel, Quislant, Ricardo, Gutierrez, Eladio, Zapata, Emilio L., Plata, Oscar
• Format: Article
• Language: English
• Subjects: Computer architecture; Concurrency control; Conflict resolution; GEMS; Hardware; hardware transactional memory; IBM power8; Instruction sets; Message systems; Parallel programming; Proposals; Protocols; shared-memory parallelism; Speculative barriers; Synchronism
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2020.3044234

Transactional Memory (TM) is a synchronization model for parallel programming which provides optimistic concurrency control. Transactions can run in parallel and are only serialized in case of conflict. In this article we use hardware TM (HTM) to implement an optimistic speculative barrier (SB) to replace the lock-based solution. SBs leverage HTM support to elide barriers speculatively. When a thread reaches an SB, a new SB transaction is started, keeping the updates private to the thread, and letting the HTM system detect potential conflicts. Once the last thread reaches the corresponding SB, the speculative threads can commit their changes. The main contributions of this work are: an API for SBs implemented with HTM extensions; a procedure to check the speculation state in between barriers to enable SBs with non-transactional codes; a HTM SB-aware conflict resolution enhancement where SB transactions stall on a conflict with a standard transaction; and a set of SB use guidelines derived from our experience on using SBs in a variety of applications. We evaluated our proposals in two different architectures with a full-system simulator and an IBM Power8 server. Results show an overall performance improvement of SBs over traditional barriers.