Comparative Analysis of Pad Geometries Used for Multi-Layer Ceramic Capacitors in Power Distribution Networks

Decoupling capacitors have already been mandatory for circuit board designs for decades, but lower supply voltages combined with higher currents required by the integrated circuits (ICs) made these passive components of higher importance. Capacitors provide a temporary source of energy from a time p...

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Bibliographic Details
Main Authors: Petre, Adrian-Razvan, Drumea, A., Pantazica, M., Marghescu, C.I.
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Frequency measurement
Geometry
Impedance
Inductance
loop inductance
mounting inductance
PDN
Printed circuits
reverse-aspect-ratio capacitors
RLC circuits
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Summary:Decoupling capacitors have already been mandatory for circuit board designs for decades, but lower supply voltages combined with higher currents required by the integrated circuits (ICs) made these passive components of higher importance. Capacitors provide a temporary source of energy from a time perspective and also a low-impedance path from a frequency perspective being essential components in Power Distribution Networks (PDNs). To achieve a certain target impedance, it is important to accurately characterize the Equivalent Series Inductance (ESL) of ceramic decoupling capacitors. Even if manufacturers give highly detailed simulation models for their parts, the ESL can easily be increased by the mounting inductance. This addition results from the VIA pair required to connect the component to the power planes of the board. In this paper, we investigate different pad geometries used for ceramic capacitors in PDNs which can increase or decrease the mounting inductance. A comparative analysis is performed based on the results and best design practices are listed in the end.
ISSN:2642-7036
DOI:10.1109/SIITME50350.2020.9292307