Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach

• Main Authors: Janwadkar, Sudhanshu, Dhavse, Rasika
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Binary Adder; Computer architecture; Field programmable gate arrays; Logic gates; Mathematics; Parallel-Prefix Adders; Power demand; Power-Efficient Adders; Signal processing algorithms; Vedic Mathematics; VLSI architectures
• ISSN: 2159-3450
• DOI: 10.1109/TENCON50793.2020.9293799

In this paper, we propose design and implementation of novel line adder architecture capable of adding multiple addends in a single step. The architecture is derived based on addition algorithm from Shuddha system of vedic mathematics. The adder architecture is particularly suitable for a class of applications, such as FIR filter, where multiple operands are required to be added. The implementation is particularly suited for portable systems where area and power consumption are highly constrained. We then quantitatively compare proposed adder architecture against popular Parallel-prefix adder architectures for different wordlengths (N = 4, 8, 16 and 32 bits). All the architectures are implemented on Genesys2 board (Xilinx part number xc7k325t-2ffg900c) using VHDL coding and Xilinx Vivado 2016.2 platform. Standard performance metrics such as FPGA device utilization (number of slices and logic LUTs), Power Consumption and Performance are considered for comparison. Results indicate that proposed vedic adder occupies 35.12 % lesser logic LUTs and 28.71 % lesser slices than any other adder architectures, under consideration, while at the same time, there is an improvement of 9.1 % in on-chip FPGA power consumption than all other adder architectures. The performance of vedic adder architecture draws parallel with that of fastest prefix adder being considered.